The present invention relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to generating phase shifting patterns to improve the patterning of gates, regions, structures, and layers needing sub-nominal dimensions.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to achieving smaller sizes of IC device features is the capability of conventional lithography. Lithography is the process by which a pattern or image is transferred from one medium to another. Conventional IC lithography uses ultra-violet (UV) sensitive photoresist. Ultra-violet light is projected to the photoresist through a reticle or mask to create device patterns on an IC. Conventional IC lithographic processes are limited in their ability to print small features, such as contacts, trenches, polysilicon lines or gate structures.
Generally, conventional lithographic processes (e.g., projection lithography and EUV lithography) do not have sufficient resolution and accuracy to consistently fabricate small features of minimum size. Resolution can be adversely impacted by a number of phenomena including: diffraction of light, lens aberrations, mechanical stability, contamination, optical properties of resist material, resist contrast, resist swelling, thermal flow of resist, etc. As such, the critical dimensions of contacts, trenches, gates, and, thus, IC devices, are limited in how small they can be.
For example, at integrated circuit design feature sizes of 0.5 microns or less, the best resolution for optical lithography technique requires a maximum obtainable numerical aperture (NA) of the lens systems. Superior focus cannot be obtained when good resolution is obtained and vice versa because the depth of field of the lens system is inversely proportional to the NA and the surface of the integrated circuit cannot be optically flat. Consequently, as the minimum realizable dimension is reduced in manufacturing processes for semiconductors, the limits of conventional optical lithography technology are being reached. In particular, as the minimum dimension approaches 0.1 microns, traditional optical lithography techniques may not work effectively.
With the desire of reducing feature size, integrated circuit (IC) manufacturers established a technique called xe2x80x9cphase shifting.xe2x80x9d In phase shifting, destructive interference caused by two adjacent translucent areas in an optical lithography mask is used to create an unexposed area on the photoresist layer. Phase shifting exploits a phenomenon in which light passing through translucent regions on a mask exhibits a wave characteristic such that the phase of the light exiting from the mask material is a function of the distance the light travels through the mask material. This distance is equal to the thickness of the mask material.
Phase shifting allows for an enhancement of the quality of the image produced by a mask. A desired unexposed area on the photoresist layer can be produced through the interference of light from adjacent translucent areas having the property that the phase of the light passing through adjacent apertures is shifted by 180 degrees relative to each other. A dark, unexposed area will be formed on the photoresist layer along the boundary of the phase shifted areas caused by the destructive interference of the light which passes through them.
Phase shifting masks are well known and have been employed in various configurations as set out by B. J. Lin in the article, xe2x80x9cPhase-Shifting Masks Gain an Edge,xe2x80x9d Circuits and Devices, March 1993, pp. 28-35. The configuration described above has been called alternating phase shift masking (PSM).
In some cases, phase shifting algorithms employed to design phase shifting masks define a phase shifting area that extends just beyond active regions of an active layer. The remaining length of polysilicon, for example, is typically defined by a field or trim mask. However, this approach is not without its problems. For example, alignment offsets between phase shift masks and field masks may result in kinks or pinched regions in the polysilicon lines as they transition from the phase shifting area to the field mask areas. Also, since the field masks are employed to print the dense, narrow lines of polysilicon beyond the active regions, the field masks become as critical and exacting as the phase shift masks.
Phase shift patterning of polysilicon or xe2x80x9cpolyxe2x80x9d layouts has been proven to be an enhancement in both manufacturing as well as enabling smaller patterned lines and narrow pitches. These items can be more enhanced as the desired linewidth and pitch shrinks, yet there can be some risks and complications.
Conventional patterning with phase shifters has been done by shifting only the areas of minimum desired dimensionsxe2x80x94usually the poly gate or narrow poly that is over the active pattern. The patterned poly lines that are away from the active regions are usually laid out with similar design rules as that of the patterned poly lines on active regions. As such, there can be many transitions between the phase shifted patterning and binary patterning. Transition areas can result in linewidth loss, increasing device leakage.
Current alternating phase shift masking (PSM) designs for polysilicon layers often focus on enabling gate shrink by applying alternating phase shift regions around the gate region (i.e., the intersection of the polysilicon and active layers). One such alternating PSM design is described in U.S. Pat. No. 5,573,890 entitled METHOD OF OPTICAL LITHOGRAPHY USING PHASE SHIFT MASKING, by Christopher A. Spence (one of the inventors of the present application) and assigned to the assignee of the present application.
An enhanced phase shift approach was developed to reduce the transition regions and move those regions away from the active edge to wider poly or corners of poly patterns where linewidth loss would have little or no impact. Examples of this enhanced phase shifting approach are described in U.S. patent application Ser. No. 09/772,577, entitled PHASE SHIFT MASK AND SYSTEM AND METHOD FOR MAKING THE SAME, filed on Jan. 30, 2001, now U.S. Pat. No. 6,534,224 issued Mar. 18, 2003, by Todd P. Lukanc (one of the inventors of the present application) and assigned to the assignee of the present application, incorporated herein by reference.
The specification of the Lukanc patent application describes binary and phase masks that define parts of the poly pattern and need to have very controlled critical dimensions (CDs). The phase mask basically has long narrow openings that are easy to pattern but the binary mask has both small openings as well as small lines, in both isolated and dense areas. As such, the patterning of the binary mask can be complicated and the manufacturing window of this technique can be limited. In both the simple phase and the enhanced phase methods, both masks are critical and have different optimized illumination and patterning conditions.
Other known systems use a xe2x80x9cnodexe2x80x9d based approach rather than a gate-specific approach to generate a phase assignment that attempts to apply phase shifting to all minimum poly geometries (both field and gate). Two examples of the xe2x80x9cnodexe2x80x9d based approach include, for example, Galan et al. xe2x80x9cApplications of Alternating-Type Phase Shift Mask to Polysilicon Level for Random Logic Circuits,xe2x80x9d Jpn. J. Appl. Phys. Vol. 33 (1994) pp. 6779-6784, December 1994, and U.S. Pat. No. 5,807,649 entitled LITHOGRAPHIC PATTERNING METHOD AND MASK SET THEREFOR WITH LIGHT FIELD TRIM MASK, by Liebmann et al.
In view of the known art, there is a need for improvements to the clear field phase shifting mask (PSM) and field or trim mask approach that result in simpler and more reliable mask fabrication and in better wafer imaging. Further, there is a need to minimize variations or use of optical proximity correction (OPC) by enclosing phase shift masking features. Yet further, there is a need to generate phase shifting patterns to improve the patterning of gates and other layers needing sub-nominal dimensions.
An exemplary embodiment is related to a technique in which a boundary region is added to the outside parallel edge of phase zero (0) pattern defining polygons as well as to outside edges of phase 180 regions. This technique can reduce the need for optical proximity correction (OPC) and improve the manufacturability and patterning process window for integrated circuits. The technique can also set the width of both phase 0 and phase 180 polygons to specific sizes, making OPC easier to assign.
The techniques of an exemplary embodiment can be particularly helpful in minimizing phase mask patterning coma effects. Due to the asymmetric design of a clear field phase shifting mask and trim, the isolated lines or last line in an array can be more susceptible to the coma effect and other aberrations. To reduce the coma effect, a small additional line or boundary region is created at the edge of phase zero structures. The width of the line can be similar to that used on the phase boundary and sufficiently thin to not print directly on the wafer.
An exemplary embodiment is related to a method designing a phase shifting mask. This method can include identifying edges of a first phase region of a phase shifting mask, expanding one side of the identified edges opposite and parallel to the side of the first phase region proximate the critical poly region to define a line, and forming a opaque line in the line along the edge of the first phase region opposite and parallel to the side of the first phase region proximate the critical poly region. The first phase region is located proximate a critical poly region and the identified edges are not edges of the first phase region adjacent to the critical poly region.
Another exemplary embodiment is related to a method of generating phase shifting patterns to improve the patterning of gates or other layers. This method can include defining critical gate areas, creating phase areas on either side of the critical gate areas, assigning opposite phase polarities to the phase areas on either side of the critical gate areas, enhancing phase areas with assigned phase polarities, defining break regions where phase transitions are likely to occur, generating polygons to define other edges and excluding the defined break regions, constructing a boundary region outside of first phase regions to form a chrome border, and constructing a boundary line along an edge of second phase regions. The edge of the second phase regions is opposite and parallel to a side of the second phase region proximate the critical gate areas.
Another exemplary embodiment is related to a method of enhancing clear field phase shift masks with a boundary line along outside edges of phase 0 regions. This method can include assigning phase polarities to phase areas where the phase areas includes first phase areas and second phase areas, defining edges of the assigned phase areas, establishing a first boundary around the added edges of the first phase regions, forming a phase shifting border in the first boundary around the first phase regions, and forming an opaque line along an edge of the second phase regions. The edge of the second phase regions is opposite and parallel to a side of the second phase regions proximate a critical poly region.
Another exemplary embodiment is related to a mask configured for use in an integrated circuit manufacturing process. This mask can include a critical poly section defined by first edges of a phase zero region and first edges of a phase 180 region, a chrome boundary region located outside second edges of the phase 180 region, and an opaque line located on a parallel edge of the phase zero region. The second edges of the phase 180 region are different than the first edges of the phase 180 region. The parallel edge is different than the first edges of the phase zero region.